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GCT Concertrator card. Overview. Carries 2 leaf cards Collects electron data Single ended electrical interface Interfaces to two wheel cards 3, 80 pair LVDS cables Standard Samtec part Interfaces to GT High speed serial (copper, non-isolated) LVDS electrical interface 9U VME form factor.
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Overview • Carries 2 leaf cards • Collects electron data • Single ended electrical interface • Interfaces to two wheel cards • 3, 80 pair LVDS cables • Standard Samtec part • Interfaces to GT • High speed serial (copper, non-isolated) • LVDS electrical interface • 9U VME form factor
System Implementation • Data Input • Accepts data from 2 leaf cards electrons and two wheel cards • Nearly 400 signals, differential • Outputs highest ranking jets, jet count and Et • 7, 1.6GBps links to GT • Processing • Two Xilinx Virtex4 FPGAs • XC4VLX100FF1513 • I/O (as opposed to logic) intensive design • Advanced Virtex4 I/O features reduce risk • Better double/quad data rate support • Improved Differential support • One for Jet sorting, one for Et electron, and Jet count • Also S-link and timing (TTC) functions
Block Diagram Jet interface 1 sorted jets = 100 unfinished jets = 40 VME J1 Header 2 x electron leaf card Jet 1 10 60 Virtex 4 XC4VLX100 11FF1513 2X130 10 LEDs VME J2 130 Slink data 2x140 80 Jet 2 80 DS92LV16 Serdes chips Virtex 4 XC4VLX100 11FF1513 2x40 Reset 80 Tx Tx 2x80 to GT Tx Tx to GT 10 20 Tx Tx to GT Header 2x160 80 Tx Jet 3 Tx to GT 60 4 Tx to GT 60 Tx Ethernet TTCrq Tx to GT Tx Tx to GT 20 Tx FMM test in Rx Rx Jet interface 2 sorted Et & jet Count = 40 Control and spare = 80 Jet interface 3 sorted jets = 80 unfinished jets = 80 headers and isolation buffers provide opportunity for alternative GT link TTC input
Test and Verification • Stand alone operation possible • USB adaptor ready for fabrication • Same module as wheel card • Modification of leaf card test board • Includes power supply and loopback • Used in conjunction with bench top supply • LabView test interface operational with leaf card • Cable loopback for wheel link • Uses production cable (straight through) • SERDES reciever allows loopback • Links to GT fully testable • Board fully testable • USB adaptor and loopback verify all signals • Assume a crate with VME controller available • Just needed for VME interface
Design resources • New Design • CERN Engineering • CERN PCB layout • CMS engineering • Responsibility shared with leaf card • Assistance from Imperial may be wise • Reduces manpower risk but adds communication overhead/coordination effort • Central PCB layout service • Outside contractor possible, if required
Risk Assessment • Virtex4 FPGAs • New devices • Highly desirable due to enhanced I/O • Improved speed and density • Conservative design requirements • May require .0201 decoupling cap scheme • Blind/buried vias, small drill diameters • .008” used extensively on leaf card • Limited high speed I/O requirements • Mature National DS92LV16 bus LVDS links • Required for interface to GT • 40 MHz single ended possible to leaf cards • 40MHz DDR differential to wheel concentrator • Considerable enhancement potential built in • Straightforward, but physically large design • Serial links proven on current design • Relies on typical, rather than best case performance • No time critical design elements relative to FPGA specs
Current Status • Schematic entry 30% complete • Virtex4 symbol created • Common part (wheel card)
Manpower and schedule • CMS engineering support • 6 months design (full time) • Layout • 3 months full time • 6 months to prototype order • 7 months to first hardware delivery • Equal priority to leaf card • Resources will be diverted from the wheel card if problems arise
