Download
lecture 3 datapath control and computer arithmetic n.
Skip this Video
Loading SlideShow in 5 Seconds..
Lecture 3: Datapath, Control, and Computer Arithmetic PowerPoint Presentation
Download Presentation
Lecture 3: Datapath, Control, and Computer Arithmetic

Lecture 3: Datapath, Control, and Computer Arithmetic

0 Vues Download Presentation
Télécharger la présentation

Lecture 3: Datapath, Control, and Computer Arithmetic

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. Lecture 3: Datapath, Control, and Computer Arithmetic

  2. Review: ALU Design • Bit-slice plus extra on the two ends • Overflow means number too large for the representation • Carry-look ahead and other adder tricks 32 A B 32 signed-arith and cin xor co a0 b0 a31 b31 4 ALU0 ALU31 M co cin co cin s0 s31 C/L to produce select, comp, c-in Ovflw 32 S

  3. Review: Elements of the Design Process • Divide and Conquer (e.g., ALU) • Formulate a solution in terms of simpler components. • Design each of the components (subproblems) • Generate and Test (e.g., ALU) • Given a collection of building blocks, look for ways of putting them together that meets requirement • Successive Refinement (e.g., multiplier, divider) • Solve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings. • Formulate High-Level Alternatives (e.g., shifter) • Articulate many strategies to "keep in mind" while pursuing any one approach. • Work on the Things you Know How to Do • The unknown will become “obvious” as you make progress.

  4. Review: Summary of the Design Process Hierarchical Design to manage complexity Top Down vs. Bottom Up vs. Successive Refinement Importance of Design Representations: Block Diagrams Decomposition into Bit Slices Truth Tables, K-Maps Circuit Diagrams Other Descriptions: state diagrams, timing diagrams, reg xfer, . . . Optimization Criteria: Gate Count [Package Count] top down bottom up Area Logic Levels Fan-in/Fan-out Delay Power Pin Out Cost Design time

  5. Simulation Before Construction "Physical Breadboarding" discrete components/lower scale integration preceeds actual construction of prototype verify initial design concept No longer possible as designs reach higher levels of integration! Simulation Before Construction high level constructs implies faster to construct play "what if" more easily limited performance accuracy, however

  6. MIPS arithmetic instructions • Instruction Example Meaning Comments • add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible • subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible • add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible • add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions • subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions • add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions • multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product • multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product • divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder • Hi = $2 mod $3 • divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder • Hi = $2 mod $3 • Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi • Move from Lo mflo $1 $1 = Lo Used to get copy of Lo

  7. operation a ALU 32 result 32 b 32 Arithmetic • Where we've been: • Performance (seconds, cycles, instructions) • Abstractions: Instruction Set Architecture Assembly Language and Machine Language • What's up ahead: • Implementing the Architecture

  8. Numbers • Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers • Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1 • Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number) • How do we represent negative numbers? i.e., which bit patterns will represent which numbers?

  9. Possible Representations • Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: balance, number of zeros, ease of operations • Which one is best? Why?

  10. maxint minint MIPS • 32 bit signed numbers:0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

  11. Two's Complement Operations • Negating a two's complement number: invert all bits and add 1 • remember: “negate” and “invert” are quite different! • Converting n bit numbers into numbers with more than n bits: • MIPS 16 bit immediate gets converted to 32 bits for arithmetic • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 • "sign extension" (lbu vs. lb)

  12. Addition & Subtraction • Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101 • Two's complement operations easy • subtraction using addition of negative numbers 0111 + 1010 • Overflow (result too large for finite computer word): • e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”

  13. Detecting Overflow • No overflow when adding a positive and a negative number • No overflow when signs are the same for subtraction • Overflow occurs when the value affects the sign: • overflow when adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive and get a negative • or, subtract a positive from a negative and get a positive • Consider the operations A + B, and A – B • Can overflow occur if B is 0 ? • Can overflow occur if A is 0 ?

  14. Effects of Overflow • An exception (interrupt) occurs • Control jumps to predefined address for exception • Interrupted address is saved for possible resumption • Details based on software system / language • example: flight control vs. homework assignment • Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons

  15. Review: Boolean Algebra & Gates • Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true • Show the truth table for these three functions. • Show the Boolean equations for these three functions. • Show an implementation consisting of inverters, AND, and OR gates.

  16. operation op a b res result An ALU (arithmetic logic unit) • Let's build an ALU to support the andi and ori instructions • we'll just build a 1 bit ALU, and use 32 of them • Possible Implementation (sum-of-products): a b

  17. S A C B Review: The Multiplexor • Selects one of the inputs to be the output, based on a control input • Lets build our ALU using a MUX: note: we call this a 2-input mux even though it has 3 inputs! 0 1

  18. Different Implementations • Not easy to decide the “best” way to build something • Don't want too many inputs to a single gate • Dont want to have to go through too many gates • for our purposes, ease of comprehension is important • Let's look at a 1-bit ALU for addition: • How could we build a 1-bit ALU for add, and, and or? • How could we build a 32-bit ALU? cout = a b + a cin + b cin sum = a xor b xor cin

  19. Building a 32 bit ALU

  20. What about subtraction (a – b) ? • Two's complement approch: just negate b and add. • How do we negate? • A very clever solution:

  21. Tailoring the ALU to the MIPS • Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq $t5, $t6, $t7) • use subtraction: (a-b) = 0 implies a = b

  22. Supporting slt • Can we figure out the idea?

  23. Test for equality • Notice control lines:000 = and001 = or010 = add110 = subtract111 = slt • Note: zero is a 1 when the result is zero!

  24. Conclusion • We can build an ALU to support the MIPS instruction set • key idea: use multiplexor to select the output we want • we can efficiently perform subtraction using two’s complement • we can replicate a 1-bit ALU to produce a 32-bit ALU • Important points about hardware • all of the gates are always working • the speed of a gate is affected by the number of inputs to the gate • the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) • Our primary focus: comprehension, however, • Clever changes to organization can improve performance (similar to using better algorithms in software) • we’ll look at two examples for addition and multiplication

  25. Problem: ripple carry adder is slow • Is a 32-bit ALU as fast as a 1-bit ALU? • Is there more than one way to do addition? • two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c1 = b0c0 + a0c0 +a0b0 3=2^2-1 c2 = b1c1 + a1c1 +a1b1 c2 = b1b0c0+b1a0c0+b1a0b0+a1b0c0+a1a0c0+a1a0b0+a1b1 7=2^3-1 c3 = b2c2 + a2c2 +a2b2 c3 =… 15=2^4-1 c4 = b3c3 + a3c3 +a3b3 c4 =.. 31=2^5-1 ... C31=... 2^32-1 Not feasible! Why?

  26. Carry-lookahead adder • An approach in-between our two extremes • Motivation: • If we didn't know the value of carry-in, what could we do? • When would we always generate a carry? gi = ai bi • When would we propagate the carry? pi = ai + bi • Did we get rid of the ripple? c1 = g0 + p0c0 2 c2 = g1 + p1c1 c2 = g1+p1(g0+p0c0)=g1+p1g0+p1p0c0 3 c3 = g2 + p2c2 c3 = g2+p2g1+p2p1g0+p2p1p0c0 4 c4 = g3 + p3c3 c4 = 5 cn n components Feasible! Why?

  27. Use principle to build bigger adders: Two-level carry lookahead G0 • Can’t build a 16 bit adder this way... (too big) • Could use ripple carry of 4-bit CLA adders • Better: use the CLA principle again! C1=c4=g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0 =G0+P0c0 P0

  28. MULTIPLY (unsigned) • Paper and pencil example (unsigned): Multiplicand 1000Multiplier 1001 1000 0000 0000 1000 Product 01001000 • m bits x n bits = m+n bit product • Binary makes it easy: • 0 => place 0 ( 0 x multiplicand) • 1 => place a copy ( 1 x multiplicand) • 4 versions of multiply hardware & algorithm: • successive refinement

  29. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 Unsigned Combinational Multiplier • Stage i accumulates A * 2 i if Bi == 1 • Q: How much hardware for 32 bit multiplier? Critical path?

  30. A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 How does it work? 0 0 0 0 0 0 0 B0 • at each stage shift A left ( x 2) • use next bit of B to determine whether to add in shifted multiplicand • accumulate 2n bit partial product at each stage B1 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0

  31. Unsigned shift-add multiplier (version 1) • 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Shift Left Multiplicand 64 bits Multiplier Shift Right 64-bit ALU 32 bits Write Product Control 64 bits Multiplier = datapath + control

  32. 1. Test Multiplier0 Multiply Algorithm Version 1 Start Multiplier0 = 1 • Product Multiplier Multiplicand 0000 0000 0011 0000 0010 • 0000 0010 0001 0000 0100 • 0000 0110 0000 0000 1000 • 0000 0110 Multiplier0 = 0 1a. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  33. Observations on Multiply Version 1 • 1 clock per cycle => ­ 100 clocks per multiply • Ratio of multiply to add 5:1 to 100:1 • 1/2 bits in multiplicand always 0=> 64-bit adder is wasted • 0’s inserted in left of multiplicand as shifted=> least significant bits of product never changed once formed • Instead of shifting multiplicand to left, shift product to right?

  34. MULTIPLY HARDWARE Version 2 • 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Multiplicand 32 bits Multiplier Shift Right 32-bit ALU 32 bits Shift Right Product Control Write 64 bits

  35. 1. Test Multiplier0 1a. Add multiplicand to the left half ofproduct & place the result in the left half ofProduct register Multiply Algorithm Version 2 Start Multiplier0 = 1 Multiplier Multiplicand Product0011 0010 0000 0000 Multiplier0 = 0 • Product Multiplier Multiplicand 0000 0000 0011 0010 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  36. A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 What’s going on? 0 0 0 0 • Multiplicand stay’s still and product moves right B0 B1 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0

  37. Break • 5-minute Break/ Do it yourself Multiply • Multiplier Multiplicand Product0011 0010 0000 0000

  38. Observations on Multiply Version 2 • Product register wastes space that exactly matches size of multiplier=> combine Multiplier register and Product register

  39. MULTIPLY HARDWARE Version 3 • 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Multiplicand 32 bits 32-bit ALU Shift Right Product (Multiplier) Control Write 64 bits

  40. 1. Test Product0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Multiply Algorithm Version 3 Start Product0 = 1 Multiplicand Product0010 0000 0011 Product0 = 0 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  41. Observations on Multiply Version 3 • 2 steps per bit because Multiplier & Product combined • MIPS registers Hi and Lo are left and right half of Product • Gives us MIPS instruction MultU • How can you make it faster? • What about signed multiplication? • easiest solution is to make both positive & remember whether tocomplement product when done (leave out the sign bit, run for 31 steps) • apply definition of 2’s complement • need to sign-extend partial products and subtract at the end • Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles • can handle multiple bits at a time

  42. Motivation for Booth’s Algorithm • Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier) + 0100 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 • ALU with add or subtract gets same result in more than one way: 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 • For example • 0010 x 0110 0000 shift (0 in multiplier) – 0010 sub (first 1 in multpl.) . 0000 shift (mid string of 1s) . + 0010 add (prior step had last 1) 00001100

  43. –1 + 10000 01111 Booth’s Algorithm Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none Originally for Speed (when shift was faster than add) • Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one

  44. Booths Example (2 x 7) Operation Multiplicand Product next? 0. initial value 0010 0000 0111 0 10 -> sub 1a. P = P - m 1110 + 1110 1110 0111 0 shift P (sign ext) 1b. 0010 1111 00111 11 -> nop, shift 2. 0010 1111 10011 11 -> nop, shift 3. 0010 1111 11001 01 -> add 4a. 0010 + 0010 0001 11001 shift 4b. 0010 0000 1110 0 done

  45. Booths Example (2 x -3) Operation Multiplicand Product next? 0. initial value 0010 0000 1101 0 10 -> sub 1a. P = P - m 1110 + 1110 1110 1101 0 shift P (sign ext) 1b. 0010 1111 01101 01 -> add + 0010 2a. 0001 01101 shift P 2b. 0010 0000 10110 10 -> sub + 1110 3a. 0010 1110 10110 shift 3b. 0010 1111 0101 1 11 -> nop 4a 1111 0101 1 shift 4b. 0010 1111 10101 done

  46. MIPS logical instructions • Instruction Example Meaning Comment • and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND • or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR • xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR • nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR • and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant • or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant • xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant • shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant • shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant • shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) • shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable • shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable • shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

  47. Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend "0" msb lsb "0" msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

  48. 1 0 S2 S1 S0 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 Combinational Shifter from MUXes B A Basic Building Block • What comes in the MSBs? • How many levels for 32-bit shifter? • What if we use 4-1 Muxes ? sel D 8-bit right shifter

  49. General Shift Right Scheme using 16 bit example S 0 (0,1) S 1 (0, 2) S 2 (0, 4) S 3 (0, 8) If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs)