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Design and Implementation of a WiMAX Baseband Processor

Design and Implementation of a WiMAX Baseband Processor. Student: 莊宜豐. Outline. Introduction WiMAX FPGA Architecture Design Transmitter Architecture Receiver Architecture Conclusions. Introduction.

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Design and Implementation of a WiMAX Baseband Processor

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  1. Design and Implementation of a WiMAX BasebandProcessor Student:莊宜豐

  2. Outline • Introduction • WiMAX • FPGA • Architecture Design • Transmitter Architecture • Receiver Architecture • Conclusions

  3. Introduction • It provides one baseband processor. First, building the models of the transmitter, the wireless channel. • Using VHDL language to design and implement the circuit. Finally, verifying the circuit on FPGA.

  4. WiMAX

  5. FPGA(Field Programmable Gate Array ) • Performance • Design Time • Design Cost • Manufacturing Cost • Short Design Time

  6. FPGA(Field Programmable Gate Array )

  7. Transmitter Architecture

  8. Receiver Architecture

  9. Frame Detection • Frame Synchronization of the (Long/Short) Preamble • (Fine/Coarse) Frequency Synchronization • Fast Fourier Transform (FFT) • Channel Estimation • Equalizer • Channel Tracking • Timing Synchronization

  10. Five steps for deriving correct the signals. The flow diagram of the receiver. (Step 1)

  11. The flow diagram of the receiver. (Step 2)

  12. The flow diagram of the receiver. (Step 3)

  13. The flow diagram of the receiver. (Step 4)

  14. The flow diagram of the receiver. (Step 5)

  15. Summary: • For step 1, this step would save a lots power consumptions. • For step 5, the proposed receiver turn four blocks off until next subframe arriving so that it also saves a lots power consumptions. • Therefore, it is more suitable for the mobile communication system.

  16. Conclusions • In this thesis, a baseband processor conforming to IEEE 802.16-2004 OFDM specifications are proposed. There are two main components in the inner receiver. • In the software simulation and prototyping measurement, all results are functionally correct and provide satisfactory performance.

  17. END

  18. Circuit Design Channel Estimator

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