Block diagram Form Factor Mezzanine card (transmitter SLINK64) Test environment Test done

1. FRL Status • Block diagram • Form Factor • Mezzanine card (transmitter SLINK64) • Test environment • Test done • Acquisition • Spy mode • Merge test • Next steps • Conclusions Dominique Gigi CMS DAQ

2. Overview Dominique Gigi CMS DAQ

3. Block diagram 64b @ 66 or 100MHz Commercial Optical Link Myrinet Lanai X 64kB IN_1 PCI connector 64-bit 64kB PCI 64b @ 66 or PCI-x 64b @ 100MHz FRL Function IN_2 FPGA 64kB Bridge IN_3 FPGA Memory 4Mbytes Compact PCI Back-plane 64b@100MHz Compact PCI 32-bit 33MHz 64kB IN_4 Dominique Gigi CMS DAQ

4. FRL form factor Place for the NIC board PCI short form factor Internal PCI bus 64bit 66MHz -Connector for NIC board -FRL FPGA -Bridge FPGA (32-bit) 2 Inputs -LVDS receivers -Buffers 64Kbytes -Connector for 2 other Inputs -FRL FPGA CompacPCI CompactPCI bus 32bit@33MHz SRAM memory (4 Mbytes) -FRL FPGA -Memory -Bridge FPGA Dominique Gigi CMS DAQ

5. Transmitter Mezzanine SLink64 protocol LVDS Altera ACEX LVDS • Generate 3 frequencies: • 40MHz from 10 to 15 meters • 60MHz from 5 to 10 meters • 80MHz <= 5 meters 1 switch to choose the frequency Dominique Gigi CMS DAQ

6. FRL Test Environment Compact PCI backplane (32b@33Mhz) Myrinet Linux + HAL software GIII FED emu. FRL Myrinet board emulated by GIII to check data and header 32 MB for Event parameters -Event # - Bunch # - FED# - Size - Time before next Event(x100ns) Dominique Gigi CMS DAQ

7. FRL receives data through connectors • GIII: • Sends event through the cable until backpressure • Sends memory address blocks • -When data is coming: • Checks Event data blocks and Headers • FRL • -Data input through Connector • -Data is sent to GIII in packets + Headers Generic III Trans. PCI 64bit/66MHz CompacPCI Dominique Gigi CMS DAQ

8. FRL spy-mode FRL to ZBT memory -1 to 1024 event(s) to spy -All event to spy Bridge/FED-kit reads data from ZBT memory and sends to PC memory (Fed-kit simplify) When ZBT memory is full - a status is added at the end (when 1 to 1024) - backpressure (acquisition mode) (when all spy) FRL Myrinet Bridge / “Fed-kit” ZBT Events FRL Bridge/ “Fed-kit” PCI CPCI ZBT Dominique Gigi CMS DAQ

9. Altera ACEX Altera ACEX 60MHz 60MHz FRL complet test for June GIII FED emul. Events FRL -first test will be done with a GIII to replace the Myrinet board Myricom FIFO 32kB ALTERA Stratrix FIFO 32kB GIII FED emul. Spy Events Dominique Gigi CMS DAQ

10. NEXT 1.Use three GIII for merger test (2 FEDs emulator-1 Test data) 2. Go to PCI –x 100 MHz 3. Correct the schematic for next production 3bis. Extender to two additional Inputs 4. Introduce the NIOS processor inside the FRL FPGA GIII GIII GIII FRL Dominique Gigi CMS DAQ

11. Conclusions • All parts of the PCB are tested • Main functions of the FRL are tested • Acquisition on each input • Spy mode through SRAM • PCI 64b-66MHz • Mezzanine transmitter board • Start to evaluate the cable length (3M cable) • 5 meters (80 MHz) • 10 meters (60 MHz) • 15 meters (40 MHz) • Pending test the maximum frequency for each length • Pending • test the 100 MHz frequency for PCIx • test with Myrinet board • Full test for June (ready for production) Dominique Gigi CMS DAQ