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Pipelined Datapath Execution and Control 18 October 2013

This document provides an in-depth exploration of pipelining in computer architecture, focusing on the mechanisms of overlapping instruction execution and instruction-level parallelism. It discusses the comparison between physical pipelines (like an automobile assembly line) and instruction throughput, emphasizing the benefits of increased speed and efficiency. The MIPS pipeline example illustrates fetch, decode, execute, memory access, and write-back stages of instruction processing. Finally, it concludes with considerations on the complexity of pipelining and prepares for the next lecture on pipeline control and hazards.

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Pipelined Datapath Execution and Control 18 October 2013

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  1. CDA 3101 Fall 2013Introduction to Computer Organization Pipelined Datapath Execution and Control 18 October 2013

  2. Pipelining • Overlapped execution of instructions • Instruction level parallelism (concurrency) • Physical pipeline: Automobile assembly line • Response time for any instruction is the same • Instruction throughput increases • Speedup = k x number of steps (stages) • Theory: k is a large constant • Reality: Pipelining introduces overhead

  3. Pipelined Datapath MEM/WB Mux IF/ID ID/EX EX/MEM Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  4. MIPS Pipeline • MIPS subset • Memory access: lw and sw • Arithmetic and logic: and, sub, and, or, slt • Branch: beq • Steps (pipeline segments) • IF: fetch instruction from memory • ID: decode instruction and read registers • EX: execute the operation or calculate address • MEM: access an operand in data memory • WB: write the result into a register

  5. Execution of lw (1/5) Instruction Fetch MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  6. Execution of lw (2/5) Instruction Decode MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  7. Execution of lw (3/5) Execution MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  8. Execution of lw (4/5) Memory MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  9. Execution of lw (5/5) Write Back MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  10. Datapath Resources Used for lw MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Instr. Mem Data Mem PC Sign extend

  11. Multiple-clock-cycle Diagram Bypass

  12. Single-cycle Diagram (Cycle 1) IF: lw $10, 20($1) MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  13. Single-cycle Diagram (Cycle 2) IF: sub $11, $2, $3 ID: lw $10, 20($1) MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  14. Single-cycle Diagram (Cycle 3) ID: sub $11, $2, $3 EX: lw $10, 20($1) MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  15. Single-cycle Diagram (Cycle 4) EX: sub MEM: lw MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  16. Single-cycle Diagram (Cycle 5) MEM: sub WB: lw MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  17. Single-cycle Diagram (Cycle 6) WB: sub MEM/WB IF/ID ID/EX EX/MEM Mux Add Shift left 2 4 Add Mux ALU Regs Mux Instr. Mem Data Mem PC Sign extend

  18. Conclusions • Caution: Pipelining is not as simple as it might appear • Different resources used per cycle per instruction • More complex than multicycle DP • Multiple representations • Pipeline contents representation • Single-cycle datapath: convenient • Single- and Multi-cycle diagrams • Instructor’s choice Next Lecture: Pipeline control and hazards

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