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CMOS DYNAMIC LOGIC DESIGN

CMOS DYNAMIC LOGIC DESIGN. Integrated Circuits Spring 2001 Dept. of ECE University of Seoul. Dynamic Logic Motivation.  Complementary CMOS Logic   V OH =V DD , V OL =GND   No Static Power Dissipation   For Fan-In of N, (2N) Transistors Required

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CMOS DYNAMIC LOGIC DESIGN

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  1. CMOS DYNAMIC LOGIC DESIGN Integrated Circuits Spring 2001 Dept. of ECE University of Seoul

  2. Dynamic Logic Motivation •  Complementary CMOS Logic •   VOH=VDD, VOL=GND •   No Static Power Dissipation •  For Fan-In of N, (2N) Transistors Required •  Series Network Unavoidable •  pseudo-nMOS Logic •   For Fan-In of N, (N+1) Transistors Required •   Series Network Avoidable •  VOLGND •  Static Power Dissipation •  Dynamic Logic •  Combination of Two Design Approaches

  3. PDN Basic Principle – fn Network •  CLK=L[PRECHARGE] •  MN OFF : Y can’t go down to GND •  MP ON : Y prechaged to VDD •  CLK=H[EVALUATION] •  MP OFF •  MN ON • Y can go down to GND • or • stay at VDD • according to PDN evaluation.

  4. PUN Basic Principle – fp Network •  CLK=L[PRECHARGE] •  MP OFF : Y can’t go up to VDD •  MN ON : Y prechaged to GND •  CLK=H[EVALUATION] •  MN OFF •  MP ON • Y can go up to VDD • or • stay at GND • according to PUN evaluation.

  5. fn Network – Operation • EVALUATION PRECHARGE

  6. VIL, VIH & VM fn Network – Characteristics •  Logic – PDN consists of nMOS Transistors •  Number of Transistors: N+2  •  Faster Switching Speed due to Reduced # of Transistors •  Ratioless Logic: VOH=VDD, VOL=GND  •  No Static Power Dissipation, Only Dynamic Power Dissipation  •  Reduced Noise Margin (NML) 

  7. fn Network – Example  4-Input NAND  Waveform tpHL How about tpLH? tpLH=0!!

  8. fn Network Problem – Leakage Current •  ILK = IRD (Reverse-Biased Diode) + IWI (Weak-Inversion) •  •  For Proper Logic Operation, VDD-DVLK > VIH

  9. Leakage Current Example •  ILK= 10nA (for example) •  CL= 32.75fF (pp. 133 in textbook) •  Leakage Ripple •  High Voltage @ Y •  VIH for Inverter • VIH=2.92V (pp. 128 in textbook)

  10. fn Network Problem – Charge Sharing •  Before A Rising, •  After A Rising, •  Charge Sharing Ripple

  11. Solution - Charge Sharing Problem

  12. might forward-bias PN junction fn Network Problem – Clock Feedthrough

  13. fn Network Problem – Cascading •  Ideally, Y = NOT(X) = NOT(NOT(A)) = A = “H” •  Non-Zero Falling Time @ X-node  Y-node Also Falling • until X-node reaches VTHN • Basic Problems: Outputs Precharged to VDD & They drives nMOSFET.

  14. DOMINO Logic •  Solve Problem of Cascading •  But Still Dynamic Logic  Leakage, Charge Sharing, Clock Feedthrough •  Can’t Make Inverting Logic such as NAND, NOR, … •  Very High Speed Operation Achievable

  15. ZIPPER Logic  Precharged to VDD (GND)  Drives pMOS (nMOS) Logic  Speed Unbalance between PDN (nMOS) & PUN (pMOS)  Higher Speed Than Domino Due to Lack of Inter-stage Inverters  DEC Alpha Processor

  16. CMOS Logic Comparison

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