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Figure 1

Figure 1. PC. Emulation System. SOC RTL. Display. Memory [Embedded SOC Software]. Protocol Interface. MMC. Keypad. Terminal. Transactor C Interface. Transactor HW Interface. Protocol Interface. Terminal. Transactor C Interface. Transactor HW Interface. Protocol Interface.

daniel-sanders
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Figure 1

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  1. Figure 1 PC Emulation System SOC RTL Display Memory [Embedded SOC Software] Protocol Interface MMC Keypad Terminal Transactor C Interface Transactor HW Interface Protocol Interface Terminal Transactor C Interface Transactor HW Interface Protocol Interface Display Transactor C Interface Transactor HW Interface Protocol Interface Camera Camera Transactor C Interface Transactor HW Interface Protocol Interface Keypad Ethernet USB Transactor C Interface Transactor HW Interface Protocol Interface USB Transactor C Interface Transactor HW Interface Protocol Interface Ethernet Transactor C Interface Transactor HW Interface Protocol Interface Audio Audio Files Transactor C Interface Transactor HW Interface Protocol Interface I/O Files Software Test Environment Interface Hardware SoC Prototype

  2. Hard Cores RAM TX RX Figure 2 ZeBu HW/SW Co-Verification Platform ZeBu Compilation Flow PC / Linux PCI I/F ZeBu Test Environment DUT [RTL] DUT Logic Emulation Resources Up to 64 Xilinx V2-8000 Memory Server Clock Server Cycle-Based Verilog/VHDL FPGA Synthesis ASIC Synthesis C/C++ SystemC Signals Reconfigurable Test Bench (RTB) ZeBu Compiler DUT Compilation Vectors Embedded Test Bench Transaction-Based RTB Generation Hardware Transactors C/C++ Logic Analyzer Dynamic Traces SystemC Channels Xilinx P&R Xilinx P&R Xilinx P&R SW Debuggers RTB Config Files DUT Config Files In-Circuit Emulation with Target System

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