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ITRS Presentation PIDS ITWG Emerging Research Devices July 16, 2003

ITRS Presentation PIDS ITWG Emerging Research Devices July 16, 2003. Jim Hutchby - SRC The Westin St. Francis Hotel San Francisco. PIDS Research Devices Working Group Participants. George Bourinaoff Intel/SRC Joe Brewer U. Florida Toshiro Hiramoto Tokyo U. Jim Hutchby SRC

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ITRS Presentation PIDS ITWG Emerging Research Devices July 16, 2003

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  1. ITRS Presentation PIDS ITWGEmerging Research DevicesJuly 16, 2003 Jim Hutchby - SRC The Westin St. Francis Hotel San Francisco

  2. PIDS Research Devices Working GroupParticipants • George Bourinaoff Intel/SRC • Joe Brewer U. Florida • Toshiro Hiramoto Tokyo U. • Jim Hutchby SRC • Mike Forshaw UC London • Tsu-Jae King UC Berkeley • Rainer Waser RWTH A • In Yoo Samsung • John Carruthers OGI • Joop Bruines Philips • Jim Chung Compaq • Peng Fang AMAT • Dae Gwan Kang Hynix • Makoto Yoshimi Toshiba • Kristin De Meyer IMEC • Tak Ning IBM • Philip Wong IBM • Luan Tran Micron • Victor Zhirnov SRC/NCSU • Ramon Compano Europe Com • Simon Deleonibus LETI • Thomas Skotnicki ST Me • Yuegang Zhang Intel • Kentaro Shibahara Hiroshima U. • Byong Gook Park Seoul N. U.

  3. Nanotubes Molecular devices Quantum cellular automata Emerging Information Processing Concepts Scope of Emerging Research Devices Bulk CMOS Double-Gate CMOS New Memory and Logic Technologies New Architecture Technologies

  4. Emerging Research DevicesIntroduction and Scope Cast a broad net to introduce readers to device and architecture concepts for information processing --- Concept --- not hardened solutions Identify --- not endorse --- and quantify Include Stimulate --- and assess/critique

  5. Emerging Research DevicesIntroduction and Scope Greatly Broadened Scope Compared to 2001 Section --- New quantitative performance metrics --- potential versus to-date performance Provide in-depth critical assessment --- key application driven questions/issues

  6. Non Classical CMOS Items - Transferred to PIDS FDSOI excluding Ultra-Thin Body SOI (tbody < 10 nm) Channel engineered transistor (a.k.a. Strained Si) Memory Item - Transferred to PIDS MRAM Architecture Item - Transferred to Assembly and Packaging 3-D Integration Emerging Research DevicesTechnology Transitioned Items out of ERD

  7. Items Transferred into Memory Floating Body DRAM (i.e., 1 Transistor - Capacitorless memory) Insulator resistance change memory Item Transferred into Logic Spin transistors Emerging Research Devices2003 Technology Transitions into ERD

  8. Bulk-Si Performance Trends Maintaining historical CMOS performance trend requires new semiconductor materials and structures by 2008-2010... Earlier if current bulk-Si data do not improve significantly. : Projected forward “Best Case” MIT Antoniadis

  9. +UTB SG +PG +UTB DG +MG +Q.Ballisttic +UTB SG +MG +Metalic J. +Strain Bulk 2019/16 2016/22 2013/32 2010/45 2007/65 2004/90 Ion required for the 17%/yr. progression Technology Enhancements for High Performance

  10. Nanotubes Molecular devices Quantum cellular automata Emerging Information Processing Concepts Scope of Emerging Research Devices Bulk CMOS Double-Gate CMOS New Memory and Logic Technologies New Architecture Technologies

  11. Fundamental Requirements Energy restorative functional process (e.g. gain) Compatible with CMOS At or above room temperature operation Compelling Motivations Functionally scaleable > 100x beyond CMOS limit and High information processing rate and throughput or Minimum energy per functional operation or Minimum, scaleable cost per function Emerging Research DevicesRequirements & Motivations for Beyond CMOS

  12. Evaluation of Emerging Research Logic Device Technologies against Technology Evaluation Criteria

  13. Emerging Technology Vectors Emerging Technology Sequence Biologically inspired Quantum computing Cellular array Defect Tolerant Architecture Spin Transistor 1-D structures RSFQ SET Molecular QCA Logic RTD-FET Insulator Resistance Change Phase Change Nano FG Floating Body DRAM SET Molecular Memory UTB-SOI Transport enhanced devices Non-classical CMOS Planar double gate Vertical Transistor FinFET Risk

  14. Observations Transistor critical dimension limited to ~ 1 nm (In the 2003 ITRS physical gate length = 7 nm for 2018) Power density, not critical dimension, limits gate density to ~ 1 x 109 gates/cm2 For the ITRS density and switching time, CMOS is approaching the maximum power efficiency Scaling Limit of Charge Based SwitchAn Example of Critical Assessment

  15. Potential solutions for device structures necessary to achieve the advanced nodes (< 45-nm) identified For the ITRS gate density and switching time - Power density (not switch size) limits charge based logic density and performance CMOS is approaching the maximum power efficiency Emerging Research Device Technologies will extend CMOS into new application domains Emerging Research DevicesSummary

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