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DESIGN OF 4-BIT ALU Fairchild Semiconductor DM74LS181

DESIGN OF 4-BIT ALU Fairchild Semiconductor DM74LS181. Prashanth Kommuri Akram Khan Gopinath Akkinepally Advisor: Dr. David W. Parent 5 December 2005. Agenda. Abstract Introduction Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions. Abstract.

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DESIGN OF 4-BIT ALU Fairchild Semiconductor DM74LS181

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  1. DESIGN OF 4-BIT ALUFairchild Semiconductor DM74LS181 Prashanth Kommuri Akram Khan Gopinath Akkinepally Advisor: Dr. David W. Parent 5 December 2005

  2. Agenda • Abstract • Introduction • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

  3. Abstract • The Aim of the project is to design a 4-bit ALU to perform 16 arithmetic and logic operations. • The circuit is designed so as to meet the following specifications: • Frequency: 200 MHz. • Power : 50 mW. • Area : 500x500 µm2 • The results are verified with AMI06 technology, Cadence tools.

  4. Introduction Why this project? • The ALU is a fundamental building block of any computing system. • Challenging to design a 15 logic level design using CMOS Technology. • Design consists of different kinds of logic… Ripple Carry Adder, Subtractor, DFF, Mux, Inv, Nand, Nor, Xor, etc.

  5. ALU Block Diagram

  6. Function Table A, B = 4 Bit Input, M , S0, S1,S2, S3 = Status Control Pin Cn = Carry in

  7. Project Summary • The ALU performs 16 Arithmetic functions and 16 Logical functions at 250MHz. • Uses Ripple carry adder to perform addition. • Design uses maximum power of 19.48mW • Maximum area is 468 x 349µm2

  8. Design Flow

  9. Gate Level Diagram

  10. Longest Path

  11. Longest Path Calculations Total Propagation delay for the longest path = 2.97ns

  12. Schematic- Top-Level

  13. Simulation 1 (Arithmetic operations)

  14. Simulation 2 (Logic operations)

  15. Layout

  16. Verification

  17. Transient Response A=1010 B=0101 S=1011 M=1 F = 0000 , F= A B

  18. Transient Response -Power

  19. Results • The ALU performs all 32 functions at a 250MHz clock and a load of 30fF. • Power dissipation is 19.48mW. • Area of the layout is 468 x 349µm2

  20. Cost Analysis • Time is money ! • Time spent on each phase is: • Design and Implementation Phase: • Logic design and NC Verilog check – 3 days. • Transistor level design and simulation – 1 week. • Floor planning and Layout – 2 weeks. • Verification and Testing Phase: • Post extraction, Power & Timing analysis – 1 day.

  21. Conclusions • Designed a 4-Bit ALU that performs 16 arithmetic and 16 logical functions at 250MHz frequency with setup and hold time 0.6ns, driving up to 30fF. • This circuit can be used as a building block for 16/32-bit ALU. • The Logic design can be modified to perform more functions.

  22. Lessons Learned • Cell based design • Uniform cell height • No bends in the poly • Floor planning • Grid pattern for Vdd and gnd • Debugging LVS errors using extracted view

  23. Acknowledgements • Thanks to our parents for their support. • Thanks to Professor David W. Parent for his guidance. • Thanks to Cadence Design Systems for the VLSI lab

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