Design of 4-bit ALU

1. Design of 4-bit ALU Swathi Dasoju Mahitha Venigalla Advisor: David W.Parent 6th December 2004

2. Agenda • Abstract • Introduction • Why • Simple Theory • Back Ground information (Lit Review) • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

3. Abstract • We designed a 4-bit ALU which can drive a load up to 40fF. • The arithmetic operations are A+B, A+B’+1, A-1,Transfer A, A+1,A+B+1,A+B’. • The logical operations are A XOR B, A AND B, A OR B, NOT A • Date should be transferred at clock frequency of 200MHz with .55ns setup and hold times. • Our design uses maximum of 15mW of Power and occupies an area of 345x310mm2.

4. Introduction • ALU is the fundamental unit of any computing system. • It consists of different kinds of logic. Full adder,Subtractor,Transfer Data,Increment, Decrement,D Flip-Flop,Mux ,Inverter,NAND ,NOR,XOR. • The knowledge of how an ALU is designed and how it works is essential for building any advanced logic circuits.

5. Block Diagram Arithmetic Unit B-INPUT LOGIC RC ADDER Bank of 12 DFFs MUX-1 Bank of 5 DFFs Logical Unit XOR AND OR INV MUX-2

6. M S1 S0 Carry In Function Carry Out 0 0 0 0 TransferA  0 0 0 1 A + 1  0 0 1 0 A + B 0 0 1 1 A + B + 1  0 1 0 0 A + B’ 0 1 0 1 A + B’ +1 0 1 1 0 A - 1 0 1 1 1  TransferA 1 0 0 X  A XOR B  X X 1 0 1 X A OR B  1 1 0 X A AND B  X 1 1 1 X  NOT A  X Function Table Depends on Inputs and Function A, B = 4 Bit Input, X = don’t care Condition M , S0, S1 = Status Control Pin

7. Project Summary • ALU is a combinational circuit that performs a set of basic arithmetic and logical operations. • The selection lines are used to determine the operation to be performed. • Our design uses Ripple Carry Adder to perform addition.

8. #LL Gate Cg to drive #Cdn’s #Cdp’s #Ln’s #Lp’s Wn Wp Cg of gate 1 NAND2 40 3 2 2 1 10 8.6 31 2 DRIVERMUX 31 3 2 2 2 5.25 9.15 24.5 3 NAND2 30 3 2 2 1 3 2.7 9.67 4 NAND2 9.67 3 2 2 1 1.8 1.5 5.59 5 INV_S 20 1 1 1 1 1.5 2.7 7.15 6 AOI_S 7.15 4   5   3  3 1.5 2.4 6.65 7 AOI_C 6.65  4  2 2    2 1.5 2.55 6.9 t = = PHL 18 8 INV_C 6.9 1 1 1 1 1.5 2.7 7.15 9 AOI_C 7.15 4  2  2  2 1.5 2.55 6.9 10 INV_C 6.9 1 1 1 1 1.5 2.7 7.15 11 AOI_C 7.15  4  2 2  2  1.5 2.55 6.9 12 INV_C 6.9 1 1 1 1 1.5 2.7 7.15 13 AOI_C 7.15  4  2 2  2  1.5 2.55 6.9 14 NAND2 30 3 2 2 1 3 2.7 9.67 15 NAND2 9.67 3 2 2 1 2.7 2.85 9.43 16 INV 9.43 1 1 1 1 1.5 3.75 8.96 17 NAND2 24.5 3 2 2 1 8.4 7.35 26.7 18 DRIVERMUX 26.7 3 2 2 2 4.35 7.65 20.4 Longest Path Calculations 5 ns .277 ns Note: All widths are in microns and capacitances in fF

9. Schematic – Top Level

10. Arithmetic Unit B-Input Logic

11. Logical Unit

12. 1select pin Mux 2 select pin Mux

13. Mux based DFF Schematic

14. 1 Bit Adder

15. 4-bit ALU layout

16. Final DRC and LVS Report

17. Simulation (Arithmetic Unit) M, S1, S0 are set for A+B’ operation. All A’s and B’s are set to 1111.

18. Simulation ( Logical Unit) M, S1, S0 are set for XOR operation. All A’s are set to 1111 and B’s are set to 0100.

19. Power Graph

20. Cost analysis • Time spent on each phase of the project • Logic design & check- 1 week . • Transistor sizing – 2 weeks. • Layouts – 1 week. • Post Extraction Check – 2 days

21. Conclusions • The ALU performs 12 functions at a frequency of 200MHz and can drive up to 40fF load. • The layout of a Ripple Carry Adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. • The delay for this circuit is nC + S, where n is the number of full adders, C is the time required to calculate (delay) an individual carry value, and S is the delay of an individual sum value. • For small adders, this delay is not very important, but for 32-bit or 64-bit computations, the delay can become significant.

22. Acknowledgements • Thanks to Professor David W.Parent for • his guidance • Thanks to Cadence Design Systems for • facilitating the use of Cadence Tools.